1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a self-alignment contact structure utilizing a selective epitaxial growth method.
2. Description of the Background Art
With an increase in a degree of integration of a semiconductor device, a wiring width has been reduced and a space width between wirings has also been decreased gradually. In order to form a contact hole to penetrate between the wirings, accordingly, a much finer pattern than the space width between the wirings in such a situation has been required.
In consideration of an overlay accuracy (=xcex1) and a dimensional accuracy (=xcex2) of a photolithographic process, C greater than 0.25xe2x88x92f (xcex1, xcex2) xcexcm is required for a size C of a contact hole required in a design rule in which the space width between the wirings is set to be 0.25 xcexcm. With an increase in the degree of integration of the semiconductor device, the size C of the contact hole exceeds the limit of microfabrication determined by a wavelength of a light source of an exposing device. f (xcex1, xcex2) is a function setting a and xcex2 to be variables.
In order to solve such a problem, a self-alignment contact technique has been utilized at the time of the manufacture of the semiconductor device having a 0.25 xcexcm rule.
In a DRAM (Dynamic Random Access Memory), the self-alignment contact technique is used most often in forming a bit line contact and a storage node contact which are formed between word lines in a memory cell array. In this case, it is important that a source/drain region of a memory cell transistor, and a bit line and a storage node are to be connected with a low resistance in any way without an electrical short circuit with a word line. The xe2x80x9cbit line contactxe2x80x9d indicates a contact plug to be connected to a bit line and the xe2x80x9cstorage node contactxe2x80x9d indicates a contact plug to be connected to a storage node of a DRAM capacitor.
With reference to FIG. 29, description will be given to a method of manufacturing a conventional semiconductor device in which the self-alignment contact technique is used. FIG. 29 is a sectional view showing a structure of the conventional semiconductor device. The semiconductor device shown in FIG. 29 has a memory cell of a DRAM, for example, and FIG. 29 shows a part thereof.
Referring to FIG. 29, in the method of manufacturing the conventional semiconductor device, an element isolation insulating film 105 formed of a silicon oxide film is first formed in a main surface of a semiconductor substrate 101, for example. Then, a p-type well region 108 to be a p-type impurity region is formed in the main surface of the semiconductor substrate 101 divided by the element isolation insulating film 105.
Next, a plurality of gate structures 160 and a plurality of source/drain regions 113a and 113b are formed. In the gate structure 160, a gate insulating film 109, a gate electrode 150 to be a word line and a cap film 112 are provided on the p-type well region 108 in this order. The gate electrode 150 has such a structure that a polysilicon film 110, a buffer film which is not shown and a metal film 111 are provided in this order.
The gate insulating film 109 is formed by a silicon oxide film, for example, and the cap film 112 is formed by a silicon nitride film, for example. Moreover, the buffer film of the gate electrode 150 is formed of WSiN, for example, and the metal film 11 is formed of tungsten (W), for example.
The source/drain regions 113a and 113b are n-type impurity regions respectively and are formed in an upper surface of the p-type well region 108 at a predetermined distance. More specifically, the source/drain regions 113a and 113b are formed in the upper surface of the p-type well region 108 interposed between the gate structures 160 which are adjacent to each other.
Next, a sidewall insulating film 117 formed of a silicon nitride film is formed on a side surface of the gate structure 160, for example. By using a selective epitaxial growth method, then, epitaxial layers 119a and 119b are formed in self-alignment on the source/drain regions 113a and 113b, respectively.
Thereafter, a silicide layer which is not shown is formed on only upper surfaces of the epitaxial layers 119a and 119b. More specifically, a titanium (Ti) film is first formed on a whole surface by sputtering and a heat treatment is successively carried out. Consequently, silicon reacts to Ti so that siliciding is carried out. By removing an unreacted titanium film, subsequently, a silicide layer is formed on only the upper surfaces of the epitaxial layers 119a and 119b. 
Next, a space between the gate structures 160 is filled and an interlayer insulating film 121 is formed over a whole surface. Then, an upper surface of the interlayer insulating film 121 is flattened. The interlayer insulating film 121 is formed by a silicon oxide film containing an impurity such as boron and phosphorus. Thereafter, a resist having a predetermined opening pattern is formed on the interlayer insulating film 121 and the interlayer insulating film 121 is selectively etched. Consequently, a contact hole 130a reaching the silicide layer provided on the epitaxial layer 119a and a contact hole 130b reaching the silicide layer provided on the epitaxial layer 119b are formed. When the interlayer insulating film 121 is to be etched, the sidewall insulating film 117 and the cap film 112 in the gate structure 160 function as etching stoppers. Therefore, the gate electrode 150 is not exposed and the contact holes 130a and 130b are formed in self-alignment.
Next, a contact plug 122a for filling in the contact hole 130a and a contact plug 122b for filling in the contact hole 130b are formed. Each of the contact plugs 122a and 122b is formed by a polysilicon film, for example. Then, an electrical connection to the contact plug 122b is carried out to provide a bit line which is not shown. Consequently, the bit line and the source/drain region 113b are electrically connected to each other through the contact plug 122b and the epitaxial layer 119b. 
Moreover, an electrical connection to the contact plug 122a is carried out to provide a storage node of a DRAM capacitor which is not shown. Consequently, the storage node of the capacitor and the source/drain region 113a are electrically connected to each other through the contact plug 122a and the epitaxial layer 119a. Then, a dielectric film and an upper electrode in the capacitor are provided.
Prior art document information related to a semiconductor device using a self-alignment contact technique includes patent documents 1 (Japanese Patent Application Laid-Open No. 6-37272 (1994)) and 2 (Japanese Patent Application Laid-Open No. 2001-44382). Moreover, prior art document information related to a semiconductor device using a selective epitaxial growth method includes a non-patent document 1 (Hideaki Matsuhashi and three others, xe2x80x9cDevelopment of 0.15 xcexcm Gate Length SOI COMS Transistor using Elevated Source/Drainxe2x80x9d, Oki Electric Industry Co., Ltd. Research and Development, October 2000, No. 184, Vol. 67, No. 3, pp. 61 to 64).
In the conventional semiconductor device having the above-mentioned structure, since a side surface of the gate electrode 150 is not exposed when the contact holes 130a and 130b are to be formed, the sidewall insulating film 117 requires a certain thickness. Therefore, it is hard to reduce the thickness of the sidewall insulating film 117. For this reason, when a space width between the word lines, that is, between the gate electrodes 150 is reduced, a contact area between the epitaxial layer 119a and the source/drain region 113a and that between the epitaxial layer 119b and the source/drain region 113b are decreased and an electric resistance between the contact plug 122a and the source/drain region 113a and an electric resistance between the contact plug 122b and the source/drain region 113b are increased.
Referring to the above-mentioned contents, in other words, when the thickness of the sidewall insulating film 117 is reduced to maintain values of the electric resistances between the contact plugs 122a and 122b and the source/drain regions 113a and 113b even if the space width between the gate electrodes 150 is reduced, the gate electrode 150 and the contact plugs 122a and 122b are electrically short-circuited if an error is made on an overlay accuracy or a dimensional accuracy in a photolithographic process in the formation of the contact holes 130a and 130b. Consequently, there is a problem in that a function operation failure is generated or the failure converges with difficulty in burn-in.
In particular, the above-mentioned problem greatly influences a performance of the semiconductor device according to a 0.13 xcexcm design rule or less in which the space between the gate electrodes 150 is remarkably reduced.
In a DRAM according to the 0.13 xcexcm design rule or less, moreover, a current driving capability is deteriorated when a channel width of a memory cell transistor is reduced. In order to cause the memory cell to carry out a stable operation, therefore, it is necessary to set an electric resistance between a contact plug and a source/drain region to be equal to or lower than that in a previous generation irrespective of microfabrication.
It is an object of the present invention to provide a technique for reducing an electric resistance between a contact plug and an impurity region to be electrically connected thereto while maintaining an insulating property between a gate electrode and the contact plug.
The present invention is directed to a method of manufacturing a semiconductor device including the steps (a) to (g). The step (a) is for forming a semiconductor substrate having a first impurity region exposed in a main surface and having, on the main surface, a gate structure including a gate electrode provided with a first insulating film on a side part thereof. The step (b) is for forming an epitaxial layer on the first impurity region so that the first insulating film lies between the epitaxial layer and the gate electrode. The step (c) is for forming a second insulating film on a side part of the gate electrode and a whole upper surface of the epitaxial layer. The step (d) is for forming an interlayer insulating film on an upper surface of a structure obtained by execution of the step (c). The step (e) is for etching the interlayer insulating film using the second insulating film as an etching stopper, thereby forming, in the interlayer insulating film, a first contact hole reaching the second insulating film provided on the epitaxial layer, the second insulating film lying between the gate electrode and the first contact hole. The step (f) is for etching the second insulating film exposed by execution of the step (e), thereby forming a second contact hole reaching the epitaxial layer in the second insulating film. The step (g) is for forming a contact plug to fill in the first and second contact holes.
Also in the case in which a thickness of the first insulating film is decreased and a contact area between the first impurity region and the epitaxial layer is increased in order to reduce an electric resistance between the contact plug to be formed at the step (g) and the first impurity region, a thickness of the second insulating film is regulated at the step (c) so that the gate electrode can be prevented from being exposed when the first contact hole is to be formed at the step (e). As a result, it is possible to reduce the electric resistance between the first impurity region and the contact plug while maintaining an insulating property between the gate electrode and the contact plug.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.